Semiconductor devices are used in integrated circuits (IC) such as computer processors, microcontrollers and memory chips. These are present in everyday electrical and electronic devices. Their fabrication involves a sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer.
The availability of metrology solutions, one of the critical factors to drive leading-edge semiconductor devices and processes, has been confronted with difficulties in advanced nodes. For developing new metrology solutions, high-quality test structures fabricated at specific sizes are needed.
Prof. Kuen-Yu Tsai and his team from the Department of Electrical Engineering at the National Taiwan University use helium ion microscopy for their research in the area of nanotechnology. Their current focus is on the design and fabrication of exploratory nanoscale integrated circuits in sub ten nanometer semiconductor nodes.
In their recent publication, the group has shown that the helium ion beam (HIB) is a potential tool to fabricate test structures for developing advanced metrology solutions in sub seven nanometer nodes. Prof. Tsai and his team spoke with us about the potential of their research and their recent publication.
What are the big issues in your research area?
As transistor density scaling continues, semiconductor manufacturing is confronted with various challenging issues. One of the critical issues is that transistors are gradually shrinking to nanoscale size. The introduction of extreme ultraviolet lithography (EUVL) also highlights the importance of defect detection in the presence of many native defects. However, due to the proximity effect, current lithography techniques such as optical projection lithography (OPL) and electron beam lithography (EBL) have their difficulties in nanoscale patterning. Therefore, it is necessary to have a beam source with a nanoscale probe size and small interaction volume with resist and substrate to develop advanced semiconductor techniques.
We demonstrated that by utilizing helium ion microscopy (HIM) direct milling, features from 100 nm down to 5 nm are readily resolved without needing any complicated process optimization, such as proximity effect correction (PEC). Additionally, the fabricated critical dimension (CD) errors are typically less than 10% show tables. Also, we have successfully fabricated the 30- and 15-nm half pitch (HP) layout patterns with programmed defects (PDs) on 50-nm Au- and 10 nm Cr-on-glass substrates, as shown in Fig. 1. This resolution is comparable to that of the best resist-based lithography published. Although the dose required to resolve HIM direct milling features is higher than that required with resist-based lithography, the process complexity is significantly reduced in HIM direct milling.
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We use the direct milling feature of the HIM to fabricate several patterns, including the smallest features down to five nanometers, without any complicated process optimization. The sub 0.5 nanometer probe size of the helium ion beam and the in situ fabrication and inspection of the helium ion microscope enable us to investigate the sub ten nanometer pattern fabrication and accelerate the research.
What do you plan to work on next?
Due to the low throughput of HIM direct-milling, we would like to combine the OPL or other high throughput lithographic techniques as complementary methods to pattern the non-critical area and leave the critical pattern to be fabricated by HIM direct-milling. Furthermore, hybrid simulation and optimization techniques of HIM and other lithographic techniques will be developed to improve the application range.